ULVAC, Inc. (hereafter, "ULVAC") made a presentation シャッフルカジノ ログインapan Institute of Electronics Packaging Annual Meeting (hereafter, "the Conference"), held at the Noda Campus of Tokyo University of Science from Wednesday, March 13 to Friday, March 15, 2024. The conference was hosted by the Japan Institute of Electronics Packaging.
The presentation was on 3D chiplet integration technology, entitled "Development of Small TSV Etching Technology Using Dual-Frequency ICP," and was awarded the "Outstanding Paper Award."
This award was given to five presentations recognized for their outstanding academic and technical merit out of 121 general presentations.
About the Japan Institute of Electronics Packaging Annual Meeting
The conference is one of the largest academic conferences in Japan on electronics packaging technology and serves as an important forum for sharing the latest research results in this field.
This year's conference, the 38th of its kind, featured presentations in a total of 22 fields, including 3D-chiplet integration, car electronics packaging, healthcare, wearable devices, and bioelectronics.
Lively discussions were held among many participants from industry, academia, and government, including both on-site and online attendees.
Details of the Award and Technology
The "Small TSV Etching Technology Using Dual-Frequency ICP" announced by ULVAC has been highly evaluated for its development of a manufacturing technology for TSV (Through Silicon Via) with a high aspect ratio and smooth sidewalls using ULVAC's original dual-frequency ICP (Inductively-Coupled Plasma) technology. This achievement led to the award recognition.
This technology improves the characteristics of small TSV, essential for stacking next-generation logic chips, and is expected to be widely applied to 3D chiplet integration technology.
The "dual-frequency ICP" technology is characterized by ICP generated using RF of different frequencies superimposed in the same space.
By using an etching system that applies this ICP, it is possible to achieve a process that simultaneously and continuously performs etching and sidewall protection for TSV, essential for 3D chiplet integration, particularly for small TSV with a diameter of approximately 1 μm.
This process achieves a level of smooth sidewall shape never seen before, without the sidewall step known as "scallop" that occurs in the conventional TSV formation process known as the Bosch method.
Furthermore, it was found that adjusting the parameters for etching and sidewall protection greatly improved the TSV shape, making it possible to create high-aspect TSV with an aspect ratio of 10 or more.
It was shown thシャッフルカジノ ログイン equipment and processes applying this new technology are effective for forming TSV with excellent characteristics, such as low leakage current, achieved by TSV with smooth sidewalls.
Future Prospects
In recent years, as AI technology has been introduced, the amount of data processed worldwide has increased exponentially, and energy consumption has increased in proportion to this.
As a result, there is an urgent need to improve the information processing capabilities of CPUs and HBM (High Bandwidth Memory) for data centers and to enhance the energy efficiency of their power consumption.
This technology is gaining attention as an important technology that supports the high performance and efficiency of these devices and is expected to be widely applied in industry.
Taking this award as an opportunity, we will further promote technical exchanges with domestic manufacturers and accelerate the practical application of this technology.
We will also continue to promote technological innovation that contributes to the development of the semiconductor industry as a whole, aiming for greater sophistication, diversification, and energy efficiency to meet customer needs.
What is 3D Chiplet Integration Technology?
3D Chiplet Integration Technology is a packaging technology that arranges, stacks, and connects multiple semiconductor chips (chiplets) manufactured using different processes in the most suitable combination.
Compared to conventional 2D packaging technology, it achieves higher density and is attracting attention as a technology that will further accelerate the evolution of integrated circuits based on Moore's Law proposed by Gordon Moore.
This technology makes it possible to build high-performance, low-power systems while maximizing the functions of each chip.
In particular, there are high expectations for its potential in next-generation processors and high-performance computing for AI and data centers.
External Links
https://jiep.or.jp/event/convention/jiep2024s/assets/docs/pdf/program.pdf
https://jiep.or.jp/event/convention/jiep2024s/index.php
https://jiep.or.jp/event/mes/mes2024/index.php
For further information
ULVAC, Inc. web_info
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